The present invention relates to flip-flop circuits operating at high speed. More particularly, the present invention relates to a flip-flop circuit including a small number of transistors and exhibiting low power consumption.
In general, a flip-flop circuit has a great influence on the area, power consumption and critical path delay of a logic circuit in a semiconductor integrated circuit. Therefore, there has been a demand for reducing the area and power consumption of the flip-flop circuit and for increasing the speed of the flip-flop circuit.
Flip-flop circuits using latch circuits which capture data during a period of a pulse width shorter than a clock cycle have been proposed to date. Hereinafter, a known flip-flop circuit having such a configuration will be described.
FIG. 13 shows a configuration of a flip-flop circuit called a semi-dynamic flip-flop (SDFF).
In FIG. 13, reference sign D denotes an input terminal, reference sign CK denotes a clock terminal and reference sign Q denotes an output terminal. Reference signs MP1 and MP2 denote PMOS transistors, reference signs MN1, MN2, MN3, MN4 and MN5 denote NMOS transistors, reference signs INV1, INV2, INV3, INV4, INV5 and INV6 denote inverter circuits, and reference sign NAND1 denotes a NAND circuit. Reference signs CKD and n1 denote nodes, reference sign IQ denotes an inner output terminal and reference sign QB denotes an inverted output terminal.
The PMOS transistor MP1 and the three NMOS transistors MN1, MN2 and MN3 are connected in series. The PMOS transistor MP1 has a source connected to a power source and the NMOS transistor MN3 has a source connected to a ground. The inverter circuits INV1 and INV2 constitute a delay circuit which transmits a clock signal at the clock terminal CK (hereinafter, referred to as a clock signal CK) to an input terminal of the NAND circuit NAND1 with a delay, and the inverter circuits INV1 and INV2 are connected in series and inserted between the clock terminal CK and the input terminal of the NAND circuit NAND1. The NAND circuit NAND1 has two input terminals, one of which is a node CKD connected to an output terminal of the inverter circuit INV2, and the other is a node n1. The node n1 connects a connection point between the PMOS transistor MP1 and the NMOS transistor MN1, an output terminal of the inverter circuit INV3 and a connection point between the PMOS transistor MP2 and the NMOS transistor MN5, together. The NAND circuit NAND1 has an output terminal connected to a gate terminal of the NMOS transistor MN1. The inverter circuits INV3 and INV4 constitute a latch circuit in which an output terminal of the inverter circuit INV3 is connected to an input terminal of the inverter circuit INV4 and an output terminal of the inverter circuit INV4 is connected to an input terminal of the inverter circuit INV3. To hold the value at the node n1, the output terminal of the inverter circuit INV3 and the input terminal of the inverter circuit INV4 are connected to the node n1. The PMOS transistor MP2 and the NMOS transistors MN4 and MN5 are connected in series. The PMOS transistor MP2 has a source connected to a power source and the NMOS transistor MN5 has a source connected to a ground. The clock terminal CK is connected to the gate of the PMOS transistor MP1, to the respective gates of the NMOS transistors MN3 and MN4, and to an input terminal of the inverter circuit INV1. As the inverter circuits INV3 and INV4, the inverter circuits INV5 and INV6 constitute a latch circuit, thereby holding the value at the inverted output terminal QB.
In U.S. Pat. No. 5,917,355 (columns 3 through 7 and FIG. 4), the inverter circuit INV7 is not used at an output stage, and the flip-flop circuit directly drives an outside component from the internal output terminal IQ. However, in order to prevent data held in the inverter circuits INV5 and INV6 from changing due to the influence of a crosstalk noise applied to the output line, or to prevent the operation speed from decreasing extremely when an output load is heavy, it is practical to drive the output load using the inverter circuit INV7. In view of this, the case where the inverter circuit INV7 is provided will be hereinafter described.
In FIG. 13, in an initial state in which the clock signal CK is at a low level, the node n1 is charged by the PMOS transistor MP1 so that a signal at the first node n1 changes to a high level. At this time, the NMOS transistor MN4 and the PMOS transistor MP2 are cut off so that the value at the output terminal Q is held at a previous value.
Subsequently, when the clock signal CK changes to the high level, a signal at the node CKD does not change to a high level immediately but is delayed by the inverter circuits INV1 and INV2 and changes to a high level. During a period in which the clock signal CK is at the high level and the signal at the node CKD is at a low level (hereinafter, referred to as an evaluation phase), the NMOS transistor MN1 is ON. Accordingly, if an input signal at the input terminal D (hereinafter, referred to as an input signal D) is at a high level during this phase, the signal at the node n1 changes to a low level due to a discharge, then a signal at the inner output terminal IQ is changed to a high level by turning ON the PMOS transistor MP2, and then an output signal at the output terminal Q also changes to a high level with a delay. On the other hand, if the input signal D is at a low level during the evaluation phase, the NMOS transistor MN2 is OFF. Accordingly, the signal at the node n1 remains at the high level and the NMOS transistors MN4 and MN5 turn ON so that the signal at the inner output terminal IQ changes to a low level, and then the output signal at the output terminal Q also changes to a low level with a delay.
Thereafter, the circuit enters a period in which the clock signal CK is at the high level and the signal at the node CKD is at the high level (hereinafter, referred to as hold phase). In this period, if the signal at the node n1 is at the high level, the NAND circuit NAND1 cuts off the NMOS transistor MN1 so that the inverter circuits INV3 and INV4 keep the signal at the node n1 at the high level without being affected by the value of the input signal D. On the other hand, in a case where the circuit enters the hold time with the signal at the node n1 at the low level, the PMOS transistor MP1 is OFF, so that the inverter circuits INV3 and INV4 keep the signal at the node n1 at the low level, independently of the value of the input signal D.
However, a study done by the present inventors shows that the known flip-flop circuit has the following drawbacks. That is to say, in the known circuit shown in FIG. 13, if the input signal D is at the high level when the clock signal CK changes from the low level to the high level to cause the circuit to enter the evaluation phase, it is necessary to hold the ON state of the NMOS transistor MN1 for a certain period in addition to turning ON the NMOS transistors MN2 and MN3, in order to ensure the high-to-low transition of the signal at the node n1. Therefore, it is necessary to provide a delay circuit constituted by the inverter circuits INV1 and INV2 on a pass along which the clock signal CK is transmitted to the node CKD. The addition of the inverter circuits INV1 and INV2 increases the number of MOS transistors constituting the circuit accordingly, so that the layout area also increases. In the case of the configuration shown in FIG. 13, the flip-flop circuit is implemented with 25 MOS transistors.
In addition, when the clock signal CK changes from the low level to the high level with the input signal D at the high level as described above, the signal at the node n1 changes from the high level to the low level. However, in a subsequent period in which the clock signal CK changes from the high level to the low level to return to the initial state, the PMOS transistor MP1 turns ON and the NMOS transistor MN3 turns OFF, so that the signal at the node n1 is fixed at the high level. Therefore, fixing the signal at the node n1 at the high level does not depend on the operation of the NMOS transistor MN1. On the other hand, the output of the NAND circuit NAND1 changes from a high level to a low level and then, after a lapse of delay time of the delay circuit constituted by the inverter circuits INV1 and INV2, the output of the NAND circuit NAND1 rises back to the high level to unnecessarily turn OFF the NMOS transistor MN1. In this manner, the known circuit shown in FIG. 13 includes the circuit operation of unnecessary power consumption.